As signals in electronic devices switch at higher and higher frequencies, delays of on-chip interconnects represent increasingly significant considerations for performance and power consumption. High frequency signaling and smaller feature sizes made possible by advanced processing techniques magnify the importance of signal timing. In order to reduce delays and/or save energy, a number of prior techniques have been tried.
Static buses are simple in design and have lower switching activity. The lower switching activity can reduce power consumption. However, speed and power consumption, of a particular interconnect segment also depend on the switching activity of adjacent wires. Unfortunately, while a wire can have a voltage transitioning in one direction each adjacent wire can have a transition in the opposite direction. This results in a coupling capacitance that is twice as large as the actual inter-line capacitance (a coupling factor of 2). Therefore, a significant worst-case delay may occur on a static bus when neighboring lines switch in opposite directions.
The effective coupling capacitance of a line is the actual inter-line capacitance multiplied by the coupling factor. Ideally, the coupling factor has a value of 1 when there is no transition in the neighboring lines, 2 when transitions occur in opposite directions and 0 when transitions occur in the same direction. For conventional static bus drivers and repeaters, the worst-case value of the coupling factor is 2, which increases worst-case delay, energy and peak supply current.
In a dynamic bus, interconnect segments precharge during one phase of the clock and conditionally evaluate in the next phase. Because all segments precharge and evaluate in the same direction, the worst-case coupling factor is reduced to 1. However, dynamic circuits require additional clock signals and have greater switching activity. The greater switching activity of dynamic circuits can consume more power than static circuits.
Another technique, static pulsed busses, employ pulse generators to send a pulse along the static bus each time there is an input data transition. Since the pulses are in the same direction, the worst-case coupling factor is the same as a dynamic bus with some of the switching activity advantages of a static design. However, additional logic and some additional delays are associated with a pulse generator and a pulse decoder.